The invention relates to data processing in cooperation with a memory and to addressing of the memory for this purpose. The invention can be used, for example, in an MPEG decoder (MPEG is an acronym for Motion Picture Expert Group).
A processor can access a memory via a memory interface in order to read data to be processed or to write data that has been processed. The processor can transmit an internal address to the memory interface. By means of this internal address the memory interface generates appropriate control signals for the memory. These control signals activate a specific memory cell corresponding to the internal address.
By way of example, it is assumed that the internal address comprises 18 bits A[17:0]. For a memory of the DRAM-FPM type the memory interface generates a page number from the 9 more significant bits A[17:9] and a column number from the 9 less significant bits A[8:0]. For a memory of the SRAM type the memory interface generates a bank selection from the fifth bit A[5] after the least significant bit, a page number from six more significant bits A[ 17:18] and the sixth bit A[6] after the least significant bit, an even/odd selection from the seventh bit A[7] after the least significant last bit, and a 64-bit word selection from the five less significant bits A[4:0].
Owing to the memory interface as described hereinbefore, a processor uses always the same communication mode, the internal address, independently of the type of memory used: DRAM-FPM or SDRAM. Such a data processing in cooperation with a memory appears to have been disclosed in the European Patent Application published under the number 0 793 390.
It is an object of the invention to facilitate the design of a device for data processing in cooperation with a memory.
The invention takes into consideration the following aspects. One means of facilitating the design is to ensure that a device can use one or more processors which have already been designed for one or more other devices. The devices may be different, for example, in the sense that they use different memories while they include processors of the same type. Let it be assumed that the devices have an architecture in accordance with the prior art described hereinbefore. In that case it suffices, in principle, to design a memory interface capable of generating, on the basis of an internal address, suitable control signals for the desired memory. Thus, the design should, in principle, only involve the memory interface.
However, the following problem may arise when a device is designed on the basis of processors already designed for other devices. It may be preferred that the device to be designed employs a data storage scheme which differs from other devices. A different storage scheme may be preferable for different reasons. For example, the device to be designed may involve a group of processors of a structure which differs from that of other devices. It is advisable to avoid that two processors use the same zone of the memory or that one or more zones are not used. A difference between the device to be designed and the other devices as regards the operating parameters can be another reason for preferring a different storage scheme. For example, let it be assumed that the devices are MPEG decoders. There are different types of MPEG decoding, each type having its own parameters and modes of operation.
According to the prior art a different storage scheme implies a different generation of internal addresses. This can only be achieved by modifying the processors. Thus, in accordance with the prior art, the design of a device on the basis of processors already designed for other devices requires a modification of these processors in the case that it is desired that the device to be designed employs a storage scheme which differs from that employed by the other devices.
In accordance with the invention a processing of data in cooperation with a memory has the following characteristic features. A processor generates a logic request. The logic request defines at least one characteristic common to a group of data. An addressing circuit generates a physical request on the basis of the logic request. The physical request defines memory addresses relating to the group of data. A memory interface effects a transfer of the group of data between the memory and the processor in response to the physical request.
Thus, in accordance with the invention, the processor indicates a certain group of data with the aid of one or more characteristics common to said data. For example, in accordance with the invention, a processor of an image processing device would indicate: xe2x80x9cplease, provide me with chrominance samples of line 10 of the current imagexe2x80x9d. The addressing circuit transforms this logic request into a physical request which defines the addresses where the memory stores these samples. Consequently, the processor need not indicate where and how the memory stores these samples. In accordance with the invention, the processor is not affected by the storage scheme and need not be modified in order to enable it to be used in different processing devices using different storage schemes. The invention consequently facilitates the design.
The invention will now be described in more detail hereinafter with reference to the drawings.